{"id":676419,"date":"2025-06-20T22:00:45","date_gmt":"2025-06-20T19:00:45","guid":{"rendered":"https:\/\/en.buradabiliyorum.com\/3d-chip-stacking-method-created-to-overcome-traditional-semiconductor-limitations\/"},"modified":"2025-06-20T22:00:45","modified_gmt":"2025-06-20T19:00:45","slug":"3d-chip-stacking-method-created-to-overcome-traditional-semiconductor-limitations","status":"publish","type":"post","link":"https:\/\/buradabiliyorum.com\/en\/3d-chip-stacking-method-created-to-overcome-traditional-semiconductor-limitations\/","title":{"rendered":"3D chip stacking method created to overcome traditional semiconductor limitations"},"content":{"rendered":"
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\n BBCube: Bumpless Build Cube. A bumpless three-dimensional semiconductor integrating technology<\/a> can address the challenges posed by traditional system-in-package (SiP) app<\/a>roaches. Credit: Institute of Science<\/a> Tokyo
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A novel power supply technology for 3D-integrated chips has been developed by employing a three-dimensionally stacked computing architecture consisting of processing units placed directly above stacks of dynamic random access memory.<\/p>\n

Toward realizing this, researchers developed key technologies involving precise and high-speed bonding techniques and adhesive technology. These new technologies can help in addressing the demands of high-performance computing applications, which require both high memory bandwidth and low power consumption with reduced power supply noise.<\/p>\n

From simple household appliances like televisions to laptops and smartwatches, electronic devices have transformed our everyday lives. Advancements in semiconductor fabrication technologies and chip packaging processes have been central to the explosive growth of these electronic devices. However, in today’s age of artificial intelligence (AI) and high-performance computing, the need for faster processors with enhanced power efficiencies remains unmet.<\/p>\n

Traditional system-in-package (SiP) approaches, where semiconductor chips are arranged in a two-dimensional plane (2D) using solder bumps, have size-related limitations, warranting the development of novel chip integration technologies. In this light, a team of researchers from Institute of Science Tokyo (Science Tokyo), Japan, has conceptualized an innovative 2.5D\/3D chip integration approach called BBCube. Furthermore, to drive the practical realization of BBCube, they have developed three key technologies.<\/p>\n

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Their research findings and outcomes were recently presented at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC)<\/a>, held from May 27 to May 30, 2025.<\/p>\n

The research team, comprising Specially Appointed Professors Norio Chujo, Takayuki Ohba and other scientists from the Institute of Integrated Research’s WOW Alliance Heterogeneous and Functional Integration Unit at Institute of Science Tokyo (Science Tokyo), Japan, initially developed a face-down chip-on-wafer (COW) process to circumvent the limitations of using solder interconnects.<\/p>\n

Utilizing inkjet technology and a selective adhesive coating method, they successfully carried out sequential bonding of different chip sizes onto a 300 mm waffle wafer with a narrow chip-to-chip spacing of 10 \u03bcm and a minimal mount loading time of less than 10 milliseconds.<\/p>\n

Explaining the precise COW process, Chujo comments, “More than 30,000 chips of various sizes were fabricated onto the waffle wafer, achieving enhanced bonding speed without any chip-detachment failures.”<\/p>\n

To enable this precise and high-speed COW process, the researchers turned their attention to addressing thermal stability issues that can affect multilevel stacking of ultra-thin wafers. By carefully designing the chemical properties, they developed a novel adhesive material that can be used in both COW and wafer-on-wafer processes called DPAS300. This new adhesive, composed of an organic\u2013inorganic hybrid structure, exhibited appreciable adhesiveness and heat resistance during experimental studies.<\/p>\n

Finally, to achieve high memory bandwidth and improve the power integrity of BBCube, the scientists employed a 3D xPU-on-DRAM architecture reinforced by a new power distribution highway. This included embedding capacitors between xPU and DRAM, implementing redistribution layers on the waffle wafer, and placing through-silicon vias in wafer lanes and DRAM scribe lines.<\/p>\n

“These innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems, while also suppressing power supply noise to below 50 mV,” states Chujo, highlighting the benefits of 3D stacked computing architecture.<\/p>\n

Taken together, the chip integration technologies developed by researchers from Science Tokyo have the potential to transform next-generation computing architectures.<\/p>\n

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More information:<\/strong>
\n\t\t\t\t\t\t\t\t\t\t\t\tBBCube 3D: Fully Vertical Heterogeneous Integration of DRAMs and xPUs Using a New Power Distribution Highway<\/p>\n<\/div>\n

\n Provided by
\n Institute of Science Tokyo
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\n Citation<\/strong>:
\n 3D chip stacking method created to overcome traditional semiconductor limitations (2025, June 20)
\n retrieved 20 June 2025
\n from https:\/\/techxplore.com\/news<\/a>\/2025-06-3d-chip-stacking-method-traditional.html\n <\/p>\n

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